1) The processor can it even if you don't believe it.
The whole POINT of the shared FPU is that either thread can use the full capasity of it, and when both threads want to use it, they fit nicely together because long latencies and data dependencies mean one thread cannot launch 2 operations every cycle.
And it was designed for 128-bit FMA operations, 256-bit AVX support is just hack added in late development phase
And the ability to launch 2 128-bit ops from single thread has been confirmed by benchmarks and AMD optimization manuals, as others have said. But of course YOUR though are better source of information than AMD's optimization manuals and benchmarks.
So, could you please stop posting crap you don't know anything about?
2) Could please try to understand what's the different between process and thread and tty to use terminology that makes some sense.
>>Bulldozer module with 2 MiB L2 is about 31mm^2.
>>2 Llano cores is about 32mm^2.
>
>People here have been begging for die plots, to measure the parts.
>The Bulldozer total die size is huge compared to Intel at the same shrink.
Other people than you have found those die plots.
here is one bulldozer die photo for you:
http://imageshack.us/photo/my-images/706/30327896.jpg/
here a K10 die photo
http://images.anandtech.com/reviews/it/ ... na_die.jpg
The Zambesi total size is huge because of the huge "uncore" part and lots of wasted space around the modules. The modules and L2 itself are not that huge, they are only slightly bigger than SB cores.
>The K10 FPU is half the total size of the core. (No cache)
>Bulldozers FPU is ~twice that size.
K10 FPU is about 28% of the size of the core, ie ~2.8 mm^2 in 32 nm.
Bulldozer FPU is about 23% of the size of the (module-l2cache), ie about 4.4 mm^2.
)..
Docela smesny,,
... 8120 95W (lidi nesmějí mít šméčka zdroje,desky apod...). Zatím mi asi z 20 procesorů co mám žádný nechcípl na vzduchu. Pouze jeden pod LN2....
