Procesory AMD 15h "Bulldozer&Bobcat"- info, testy, spekulace

[maltra]

maltra dajme tomu, ze je to pravda, ale ktore ES? B0, B1, B2 alebo pre vsetky. OBR hovoril, ze ziadny rozdiel medzi B0 a B2 nie je...

To chces odo mna vediet vela Thanatos, to som sem postol len ako dalsiu z pripadnych moznosti ako by sa mohol vykon predajnych verzii lisit od ES. Mohlo by to byt vyriesene aj tak ze AMD po oficialnom uvedeni a rozposlani Bulldozerov recenzentom vypusti nejaky finalny kod alebo BIOS alebo nech si to nazve kazdy ako chce. Dufam ze uz onedlho uvidime. OBR hovoril, OBR hovoril ...mozem sa kludne mylit, ale ja si nemyslim ze on mal v rukach to co nakoniec pojde do obchodov.

EDIT:

maltra to som nemysel len pre teba a viac menej som si odpovedal na svoju otazku hned vo vlastnom prispevku.

Prepac Thanatos ak to vyznelo napisane nejakym blbym tonom, tak to nebolo myslene. Dal som tam smajla.

[THANATOS]

maltra to som nemysel len pre teba a viac menej som si odpovedal na svoju otazku hned vo vlastnom prispevku.

[maltra]

Tak zeby 26. Septembra? Su to sice serverove Bulldozery, ale snad by mohli desktopy nasledovat hned za tym.

http://www.pcmag.com/article2/0,2817,2390410,00.asp

[flanker]

Its far more complicated than that. Read my Bulldozer preinfo thread at sweclockers and use translator. Yes indeed, it,s a deep piped microarchitecture but very efficient. With it, s module structure allowing the whole front-end and L2 feed one core, IPC will be higher. the branchpredictor and fetch unit is far more accurate and powerful. With Turbo and all other improvements like new IMC and so on, I think you should be ready for some impressive performance in all aspects.

http://www.xtremesystems.org/forums/sho ... ost4943563

[THANATOS]

flanker To hovorili aj iny pred nim a vtedy si bol skor pesimisticky ako optimisticky co sa stalo , vies nieco co mi nie

[ArgCZ]

z čeho usuzuješ že je optimista? Že sem dal copy/paste z xtremesystems ? Mě spíš přijde že ty se chytáš kdejakého náznaku... takovej snílek

[yuri.cs]

Its far more complicated than that. Read my Bulldozer preinfo thread at sweclockers and use translator. Yes indeed, it,s a deep piped microarchitecture but very efficient. With it, s module structure allowing the whole front-end and L2 feed one core, IPC will be higher. the branchpredictor and fetch unit is far more accurate and powerful. With Turbo and all other improvements like new IMC and so on, I think you should be ready for some impressive performance in all aspects.

Proc ne, ale stale se zapomina na to, ze hodne veci je jednodussi a latence znacne vyssi. Frekvence ale zas tak vysoka neni - 3.4 SB / 3.6 BD. Turbo u AMD je jedna obrovska neznama. Atd. Zkratka si vybral jen to pozitivni, nebo ne?

[del42sa]

deep pipeline...ze by naznak vyraznejsiho prodlouzeni pipeline oproti PhII?

[THANATOS]

ArgCZ Chytat sa nicoho nemusim, lebo o tychto vylepseniach som uz davno vedel .

yuri.cs neda sa nejako odsimulovat aky vplyv ma zhorsena latencia na vykon? Vela sa hovori o prefetch, to moze z casti eliminovat vyssie latencie, kto vie.

del42sa prehana, nemyslim si, ze BD bude mat viac ako 18 stupnov a mozno ani tolko.

[THANATOS]

28nm pre 5 modul
http://semiaccurate.com/forums/showpost ... tcount=863

[flanker]

no to bych čučel, kdyby vydaly Piledriver na 28nm řekněmě mezi Q2-Q3 2012 (tedy rok po FX první generace)

[yuri.cs]

Nu, takze ona roadmapa s halfnode 28nm SOI/SHP byla pravdiva. Dost zajimave.

//Zmena planu od Q4 '10: http://www.diit.cz/data/images/68306.jpg

//Charliho shrnuti GloFo konference. Stale spatna vyteznost u Llana.
http://semiaccurate.com/2011/09/06/what ... m-process/

[del42sa]

THANATOS: prehana, nemyslim si, ze BD bude mat viac ako 18 stupnov a mozno ani tolko.

a jak to víš ?

[THANATOS]

del42sa

a jak to víš ?

Preco, cakas viac ako 18? 18 stages by bolo 50% narast ako K10(12).

[webwalker]

THANATOS: prehana, nemyslim si, ze BD bude mat viac ako 18 stupnov a mozno ani tolko.

a jak to víš ?

Už to tu postnul yuri:

The minimum branch misprediction penalty is 20 cycles in the case of conditional and indirect branches and 15 cycles for unconditional direct branches and returns.

Takže pipe by neměla být hlubší jak 20, spíše o něco méně.

PS: Netvrdil někdo z AMD, že bude vycházet každý rok s novým/vylepšeným cpu?
PS2: Už to tu bylo?
http://www.xbitlabs.com/news/cpu/displa ... ineup.html
http://www.xbitlabs.com/news/cpu/displa ... &width=850

[del42sa]

branch prediction. The total performance penalty due to branch mispredictions
is the product of the branch misprediction rate and the
branch misprediction penalty. A single misprediction in the Alpha
21264 results in a minimum of 7 wasted cycles. The Intel Pentium
4 has a minimum of 20 cycles misprediction penalty; the
Prescott core has increased this penalty to 31 . In reality, however,
the misprediction penalty is often much larger. This is because
branches can take an arbitrarily long time to resolve in an out-of-order
pipeline. While other research focus on reducing the branch misprediction
penalty, this dissertation concentrates on reducing the number of
mispredictions.

tak to docela reálně vypadá na těch 20 stages pro BD. Takže ty řeči o "Pentiu 4" od AMD zase nebyly tolik mimo

alespoň když vezmu v úvahu jak se toto číslo mění s ohledem na délku pipeline u P4:

Willamette a Northwood měly 20 stages pipeline (jejich min. miss prediction penalty bylo také 20)

Prescott a Cedar Mill pak 31 stages (jejich min. miss prediction penalty byla 31)

BD by tedy měl mít také 20 stages (The minimum branch misprediction penalty is 20 cycles..)

[webwalker]

Dal42sa: Ano, v souvislosti s hloubkou pipeline právě jde o tu missprediction penalty (naznačuje také délku pipe).
U P4 však byl, dle mých poznámek, tenhle problém:

Branch mispredictions are much more expensive on the P4 and P4E than on previous
generations of microprocessors. The time it takes to recover from a misprediction is rarely
less than 24 clock cycles, and typically around 45 µops. Apparently, the microprocessor
cannot cancel a bogus µop before it has reached the retirement stage. This means that if
you have a lot of µops with long latency or poor throughput, then the penalty for a
misprediction may be as high as 100 clock cycles or more. It is therefore very important to
organize code so that the number of mispredictions is minimized.

[del42sa]

to ale asi byl velmi specifický případ ne ? Jinak velmi podrobně se o tom píše v tomto pdf

http://users.elis.ugent.be/~vdesmet/phd-Desmet.pdf

ale to už je poměrně hodně odborný rozbor ...

The downside of a long pipeline is that when a program branches, the processor cannot know where to fetch the next instruction from and must wait until the branch instruction finishes, leaving the pipeline behind it empty. In the extreme case, the performance of a pipelined processor could theoretically approach that of an un-pipelined processor, or even slightly worse if all but one pipeline stages are idle and a small overhead is present between stages. Branch prediction attempts to alleviate this problem by guessing whether the branch will be taken or not and speculatively executing the code path that it predicts will be taken. When its predictions are correct, branch prediction avoids the penalty associated with branching. However, branch prediction itself can end up exacerbating the problem if branches are predicted poorly, as the incorrect code path which has begun execution must be flushed from the pipeline before resuming execution at the correct location.

In certain applications, such as supercomputing, programs are specially written to branch rarely and so very long pipelines can speed up computation by reducing cycle time. If branching happens constantly, re-ordering branches such that the more likely to be needed instructions are placed into the pipeline can significantly reduce the speed losses associated with having to flush failed branches. Programs such as gcov can be used to examine how often particular branches are actually executed using a technique known as coverage analysis; however such analysis is often a last resort for optimization.

[webwalker]

No to už je hodně odborné
Já chtěl jen říci, že missprediction penalty pro BD bude v nejhorším případě 20c, což naznačuje hloubku pipe <=20 stage, kdežto u P4 (při podobné hloubce pipe) v nejhorším případě šlo klidně i o 100c. Takže srovnávat BD a P4 asi není moc přiměřené.

[del42sa]

ale to může být klidně podobné i u BD při špatném odhadu, už proto se to nazývá minimum penalty .. Právě to minimum nastává v ideálním případě, pokud odhad byl korektní a žádná z provedených operací se nemusela zahodit... Vetšinou to může být právě naopak více než těch 20, ne méně