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webwalker píše:del42sa: Pokud jsem dobře koukal, tak žádný job pro ARM specialisty

PS: Tak kdopak z nás "chytráků" se tam přihlásí?

Having a look with the Bulldozer die photos in Paint.net, if all of the 'white space' was removed and the die components fitted perfectly together (which I realise is not possible, but Gulftown is much closer to doing so) the die size of Bulldozer would be around 231 mm2 (although that is possibly excluding the decap ring).
Quite a difference from the 315 mm2 die we have now

Well in theory gate first has both lower yields and HIGHER gate density, so something definitely went wrong to end up that big. Theoretically gate first being higher density than Intel's bulk 32nm, they should have been aiming for a chip, what, 5-15% bigger than SB. 995mil transistors x 1.2 = almost 1.2billion transistors,, so 216mm2 = 1.2 = 260mm2, but if its higher density, or SHOULD be and was almost the entire reason for sticking with gate first.... then you're looking at 260mm2 -10-15% , so 233mm2 or below?

Clearly it isn't there, but from Anandtech there isn't an indication which side went wrong, at all.

Or, most importantly, Llano density is immense, though I don't know enough about it, l3 is lower density than the rest of the core, so without L3 its artificially high? Can anyone work out where it would be with equivilent l3 to sandybridge, roughly speaking, is it still massively higher density than Bulldozer or Intel 32nm?

if so, is low yields on Llano due to high density, and Bulldozer/trinity "fixes" are simply lowering the density significantly?

EDIT:_ more interestingly is the increase yields, by making it 35% bigger(a theoretical 233mm2 Bulldozer being pushed to 315mm2) if that is increasing yields, how damn bad are yields on Llano that increasing the size that much still results in more cores per wafer, ouch. That is making a lot of assumptions though

So first of all, the 2B number makes no sense whatsoever. A few months ago I was talking with Peter Glaskowsky, and I couldn't even come close to 2B. At best I was short by 25%.

The new 1.2B estimate is much closer to reality, but is it fully accurate? I don't know.

The ISSCC papers describing bulldozer are clear - a module is 213M transistors. The L3 cache uses 6T cells.

So the right way to think about the overall chip is:

Modules + L3 + Northbridge + PHYs

1. Modules are estimated at 213M, based on an ISSCC paper. Note that this paper may be outdated. For example, a new revision might have fewer devices.

2. The L3 is 8MB and should be AT LEAST 432M transistors for the data arrays. That is calculated as 6T/bit * 9bits/Byte * 8MByte. However, the tag array will also need transistors.

3. The northbridge will have few transistors, since it's mostly wiring. Tukwila has around 150M transistors, but I bet Bulldozer is half that, so call it 70M devices.

4. The PHYs will have even fewer transistors. Again, Tukwila had 40M transistors for I/O logic, so perhaps 3/4 of that, or 30M devices in Bulldozer.

Put that all together and we get:

4*213 + 432 + 70 + 30 = 1.38B transistors.

So there's a discrepancy of ~180M transistors between my estimate and AMD's number.

That doesn't mean that AMD is wrong. My estimates for northbridge or I/O could be off, but even if the numbers were 0, there would still be an issue. A more likely culprit is that the device count in the ISSCC paper is old.

Another possibility is that AMD's numbers might exclude certain transistors (e.g. redundancies). Bonus points go to Scott Wasson for this suggestion, although I don't think that could really impact more than 10-20M transistors.

So I think someone ought to ask AMD to provide a more detailed transistor break down according to the various regions of the chip. That should clarify any ambiguity.

David

Update August 30, 2011, 9:36PM Pacific - We have received word from GlobalFoundries and SOITEC that the statements made today during press luncheon ended up sounding different than what was meant. As we expected, GlobalFoundries remain comitted to SOI (as we all expect) for the process nodes in which SOI makes sense, i.e. high performance silicon nodes, such as 22nm, 14nm, 10nm and beyond.

del42sa píše:tohle by mohlo AMD/GloFo hodně pomoct, vzhledem k tomu že nedokáží dohnat Intel na poli 3D tranzistorů. http://semiaccurate.com/2011/12/07/suvo ... ransistor/

tato technologie umožňuje dosáhnout podobných výsledků jako tri gate i s planárními tranzistory.