Procesory AMD 15h "Bulldozer&Bobcat"- info, testy, spekulace

[Michael24]

V tom je právě ten háček, nikdo neví, co si má představit pod tím "capable"

[flanker]

Llano mu však jede skoro na 4700 MHz...I Cinebenche, čili tam to vypadá dobře. ALe přeci jen, je to "pouze" quad a upravená osvědčená architektura

[ttxman]

nebylo nekde jak dlouhou bude mit bulldozer pipeline? K dosazeni vysokejch taktu asi bude delsi, jen by me zajimalo o kolik.

[flanker]

zkus prohledat historii, ale delší je, bohužel taky nevím konkrétně

[ttxman]

Prave ze sem cisla nikde nenasel. Jenom odhady +30-50% delka .. to je min informaci nez s tema frekvencema.

[yuri.cs]

Myslim, ze tahle hodnota jeste nikde zminena nebyla.
Bobcat ma 15 urovnovou. 'K10' 12, Nehalem 16, Willmate 20 stages. Takze docela pravdepodobne mezi 15 a 20.

[Mckenzie]

V rozboru architektury na PCtuningu je psáno 17 ale je tam i uvedeno, že CPU bude mět integrovaný řadič PCI-E

[yuri.cs]

V rozboru architektury na PCtuningu je psáno 17 ale je tam i uvedeno, že CPU bude mět integrovaný řadič PCI-E

Pokud myslis tenhle skvost, tak to pak je urcite na 100% pravda...

Architektura samotná je optimalizována pro vysoké frekvence, čehož bylo dosaženo hlavně zkrácením instrukční pipeline. Současné procesory mají 23 stupňů, budoucí procesory by měly být vybaveny pouze 17-ti stupňovou pipeline. Kratší pipeline dokáže udržet akceptovatelné latence a efektivní komunikaci mezi zdroji i při vysokých taktech.

(17 by mela byt FO4 BD vcetne doprovodnych "jevu" a 23 pro 'K10'. Bylo zameno max FO4 jedne stage a pocet stages...)

A ano, na dieshotu BD je PCIe radic.

[ttxman]

Proc by nemohl mit PCIe radic? me to pripada jako celkem rozumny. Stejne se ten northbridge s CPU slouci a nebude to tak dlouho trvat. A PCIe je hodne efektivni na pocty dratu, ktery je potreba tahnout, takze to vypada na idealni zacatek. Jenom na to budou potrebovat novou patici a ne AM3..

[del42sa]

bulldozer had been confirm to have 22 stage pipeline(at least) with only 16kb data per module(8kb per core) and share 64kb instruction cache(or 16uops trace cache) for entire processor while having gigantic 2mb l2 per module and 12mb share l3 for all cores is opposite to intel's larger dedicate core with 64kb l1 + 256kb l2 per core with 8mb l3 share cache and 14 stage pipeline. intel had learn from their mistake and stick with 14 stage pipeline ever since conroe released. until now nehalem and upcoming sandy bridge are all 14 stage pipeline design while bulldozer is completely opposite in architecture.

http://www.tomshardware.co.uk/forum/pag ... l#t2213994

[THANATOS]

del42sa to sa mi nezda, L3 cache 12MB, nie nahodou 8MB?

P.S. nevies dat link?

[DOC_ZENITH]

bulldozer had been confirm to have 22 stage pipeline(at least) with only 16kb data per module(8kb per core) and share 64kb instruction cache(or 16uops trace cache) for entire processor while having gigantic 2mb l2 per module and 12mb share l3 for all cores is opposite to intel's larger dedicate core with 64kb l1 + 256kb l2 per core with 8mb l3 share cache and 14 stage pipeline. intel had learn from their mistake and stick with 14 stage pipeline ever since conroe released. until now nehalem and upcoming sandy bridge are all 14 stage pipeline design while bulldozer is completely opposite in architecture.

Hmm, tohle přesně měl Netburst. Ultra malou L1 cache, a dlouhou pipeine. Ano to všeobecně umožní dosažení větší frekvence. Daní za to ale je, že aby se pipeline naplnila a byla efektivní, musí bejt strašně efektivní prefetch a aplikace si s tim musí sednout. Extrémě špatné to bylo v hrách, celkem OK v enkódingu. Ale slabost netburstu v hrách pramenila také z toho, že jeho FPU běžela na poloviční frekvenci hlavního jádra.

[del42sa]

del42sa to sa mi nezda, L3 cache 12MB, nie nahodou 8MB?

P.S. nevies dat link?

z preview Buldozeru na pct:

Kromě čtyř Bulldozer modulů s osmi jádry, bude v čipu umístěna L3 cache, jejíž maximální hodnota nebyla zatím prozrazena. Některé zdroje uvádí 2MB jiné 3MB pro jeden modul, tedy v případě osmijádra bude kapacita sdílené L3 Cache 12MB nebo 8MB.

[THANATOS]

del42sa aha vdaka, davalo by logiku preco BD ma vacsiu plochu ako Gulftown.

P.S. teraz som len zistil, ze Gulftown ma len 256KB na jadro L2 cache, tak sa ani necudujem ak bude BD vacsie aj pri 8MB L3 cache.

[flanker]

tam je to jasné již...je dávno potvrzené, že L2+L3=16MB v přípa osmijádra. Nešířil bych již nesmyslné zprávy.

[del42sa]

je pravda že to preview je z minulého roku stejně jako rozbor architektury Bulldozer a jen to vysvětluje proč diskutujíci použil těch 12MB L3.Dle posledních screenů z CPU-Z to je opravdu jen těch 8MB L3 ovšem podstatný je ten rozbor BD architektury a ne to jestli má 8 nebo 12 MB L3 Cache. V podstatě , jak to trefně označil jeden z diskutujícich se jedná o AMD verzi "Pentia 4".

there's no telling why amd decide to move to longer instruction pipeline and smaller cache after seeing intel fail with their netburst architecture. one thing for sure they are decide to fight another gigahertz war and multi threading ability after amd fail compete in single thread performance since conroe released in 2006 due to inferior in architecture compare to intel's conroe and nehalem. amd had to make a break through and also make them look different from intel. that is where it give birth of bulldozer. it is mainly design for server market that's purely to run multitasking. however limited to current die size and fabrication the number of core are increase very slow during each generation. first commercial dual core was introduce in 2004 and now we just just start taking advantage from it while quad core and six core still in the air with expansive price and ran very hot by the physical limit. to having more core number without having huge die the only way is to shrink the core itself. to do so the core has to be as small as possible, means the cache must be first to throw a way then the computing unit like mpu and aux will be cut off to maintain the core size and all cache will be "uncore" and run out side the core speed. then to rise the efficiency for their smaller core inside bulldozer the only way to achieve is insanely clock speed. so the stage pipeline will be much longer in order to clock up even higher.
Result, an AMD version of pentium 4 is stand right front of you

[ttxman]

Mno kdyz to vezmes do detailu tak P4:
1) 31 stages - dlouha pipeline - problemy obecne
2) strasne mala L1 cache (8kB data jak na 486tce ) + 12k mikroinstrukci v programovy casti
3) absence L3 aspon v prvnich generacich. (i kdyz tam bejt mela...), asi doufali, ze s tema ramkama nebude potreba..
4) absence barrel shifteru - dopad na spousta vypoctu, bitovy masky atd. (vicebitovy posun trva vice taktu)
5)podivnej dekoder instrukci - 1 dekodovana instrukce na takt (taky krok zpatky P3 meli minimalne 2 dekodovany instrukce za takt (mozna 3?)) resit to mela Trace cache, jenze jeji efektivita byla v znovuzpracovani spatne odhadnutyho kodu, kdyz bylo nutny nacist kod z L2 cache nebo z ramky tak se L1 v mikroinstrukcich plnila moc pomalu na to aby pouziti mikroinstrukci prineslo nakou vyhodu (v nejhorsim pripade to ani nestacilo zasobovat ty double pumped ALUs, natoztak delat naky zasoby dopredu)
6)rozklad instrukci do vic mikroinstrukci nez P3. (vic taktu na instrukci - znatelny pokles IPC, kdyz se vysype pipeline trva to jeste dyl nez jenom jeji samotny prodlouzeni) (u CORE architektury se pak intel chlubil jak nektery mikroinstrukce vykonaji cinnost dokonce nekolika x86 instrukci najednou.. to je otocka)
7) double pumped ALUs (mame super rychlou architekturu co kdyby sme nechali ALU bezet na 2nasobny frekvenci? Zabije to maximalni frekvenci cipu, ale co v kodu nejsou zadny slozity FPU instrukce. Aneb skoro 8GHz, pak se divte tem recem o 10GHz skoro to tam bylo)

Mno na vic si uz moc nevzpominam. Ted je otazka co si z toho BD zopakuje (doufejme ze nic) a jaky budou novy problemy...

[yuri.cs]

bulldozer had been confirm to have 22 stage pipeline(at least) with only 16kb data per module(8kb per core) and share 64kb instruction cache(or 16uops trace cache) for entire processor while having gigantic 2mb l2 per module and 12mb share l3 for all cores is opposite to intel's larger dedicate core with 64kb l1 + 256kb l2 per core with 8mb l3 share cache and 14 stage pipeline. intel had learn from their mistake and stick with 14 stage pipeline ever since conroe released. until now nehalem and upcoming sandy bridge are all 14 stage pipeline design while bulldozer is completely opposite in architecture.

Ach jo...
Tak zbezne: L1D neni sdilena v ramci modulu; L1I neni sdilena v ramci procesoru!; L0 aka trace cache?; 2MB L2 neni tak giganticka, kdyz se rozdeli mezi 2 jadra; Nehalem nema 14 stages ale 16, ...

Na zaklade tohohle postu tomu numeru moc neverim.

//AMD se snazi jit po frekvenci uz HODNE davno. Viz. comp.arch, kde je receno, ze jedna iterace zrusene K9 mela mit FO4 13. BD 17.

[del42sa]

uvidíme:

Because intel did not do the same thing than what AMD is doing.

Bulldozer increases pipeline length moderately, like 40-50%.

P4 increased pipeline length more than 100%.

And the major reason for P4(willamette, northood)'s small IPC was not long pipeline itself, but other design choices:

1) Very small L1D cache(to achieve low latency with high clock speed). Bulldozer has twice bigger L1D(per core, meaning 4 times more L1 capacity per thread than nortwood with HT enabled), and better memory reordering for cases where it misses.

2) L2 cache with too small block count (small size combined to big block size). Bulldozer has 8/4 times more L2 cache blocks / core, or 16/8 times more cache blocks per module than P4(willamette/northwood)

3) P4's replay mechanism often ruined performance. (especially it ruined SMT/HypeThreading performance). AFAIK bulldozer will also have some kind of replay mechanism, but it's not needed as often as P4's replay so it's impact on performance will be much smaller ( and there is not SMT for integer code in bulldozer so it cannot disturb that )

4) High clocked mini-ALU's with lowest bits aligned to different clock edge than highest bits, which added lots of delays when data had to go away from the mini-ALU's (like for shifting and multiplication, which made those instructions very slow). Bulldozer puts the whole integer core into one place and same clock domain, all integer operations are relatively fast and overheads occur only when moving data to FPU (where there are always longer latencies anyway)

Presscott is a different story:
Presscott fixed 1 and 4 of those, and helped 2, but increased pipeline much more, having pipeline stages which are almost half of even Bulldozer's pipeline stage length, one third of P6/K7 pipeline stage length.

\\ Yuri: jenže jestli Nehalem má 16 stage ppl, tak 17 u Bulldozeru není tak velký rozdíl a těch 22 mi přijde tak akorát, respektive odpovídá to tomu prodloužení pipeline oproti K10 (12stage) o 40- 50% ....

[yuri.cs]

Takze skok ze 12 na 22? No, nezbyva nam, nez si pockat.