http://www.donanimhaber.com/islemci/hab ... D-6550.htm
Ako keby to na BD neplatilohlavne muzes obrovskou cast zmetku dale uplatnit.
Moderátoři: flanker, Eddward, Baneshee

Ako keby to na BD neplatilohlavne muzes obrovskou cast zmetku dale uplatnit.






No já netvrdím že K8 byla málo inovativní, spíš to naznačuje jak moc dobrá byla na tu dobu architektura K7. K 7 měla velmi silnou FPU a vysoký počet instrukcí na takt.Z toho těžila i K8, která navíc přidala rychlejší odezvu díky integrovanému řadiči operační paměti a 64 bit registry.Nebýt počátečních problému se SOI výrobním procesem, tak tu možná byla i o rok dříve. (2002)yuri.cs píše:Nu, jeste rekni, ze K8 byla malo inovativni.
'K10' mela sice prijit driv, namisto preslaopvani na miste s AM2/DDR2. Tez nemely lpet na monolitu, atd. Ale to jsou kdyby.
Sandtiger/Bulldozer mel prijit v 3Q 2009, to by se nikdo asi nezlobil. Ale proste zmizel z roadmap. Nahrazen byl 45nm Opterony.
http://www.hardocp.com/article/2007/07/ ... _revealed/The statements that most needs to be focused on are, “Continued Scaling for single-thread performance,” and “Partitioned for future scalability and modularity.” That would tell me that Bulldozer could be morphed according to the importance of the application whether it has specific multi-thread needs or single thread needs and still take advantage of all its resources. Currently using our dual and quad core processors, when we have a resource-hungry single threaded application, which is still usually the case, our other core(s) are sitting there doing nothing. Bulldozer seems to be able to unite its core to work together on a single threaded application. As for the “partitioned” statement I would have to read into that the heart of Bulldozer is somewhat akin to AMD’s M-SPACE design methodology in that it could be very possibly for AMD to build Bulldozer cores designed for specific applications and hardware.





Ten clanek je z roku 2007. Jeste snad na zacatku 2010 se vedelo jenom to, ze BD je 4-way. Takze nejaka relevance nulova. K tem spekulacim se da proklikat, ale chapu, 160 str je dost.del42sa píše:Bulldozer seems to be able to unite its core to work together on a single threaded application
http://www.hardocp.com/article/2007/07/ ... _revealed/

tak by vydali jen čtyřjádro do desktopu a 8jádro pro servery... Na OBRovu oblíbenou Fermi se to stejně tou spotřebou nechytáTen 45nm BD by zajimal asi vicero lidi. Kazdopadne 16 jader na 45nm, kdyz OBR tvrdi, ze i ten 32nm zere jak michacka?

http://blogs.amd.com/work/2010/10/04/20 ... ns-part-4/ 2. Q/A“How much resemblance does your today’s Bulldozer architecture have to the original design?” – Tye
As you are aware, when we initially designed “Bulldozer,” we were working with a more modular processor design. The original “Bulldozer” design was 45nm. But as development progressed, it became clear that the 45nm design that we had been working on was not going to be as competitive as we would have liked.
...
We obviously aren’t going to get into specific design changes, but we think that the 32nm “Bulldozer” can bring a lot of benefit to our product due to smaller transistor size (which can help drive down the power envelope). By going for lower power, we hope to give you more room for compute cores, FP capabilities and more.

Ne, neplati aspon ne v takove mire jako u llana.THANATOS píše:Ako keby to na BD neplatilo

Akoze nie, praveze este viac alebo myslime na ine veciNe, neplati aspon ne v takove mire jako u llana.

S casti o BD mas relativne pravdu. S casti o llanu ne. To ze se na llanu vyskytne chyba na IGP neznamena problem, ale jen dalsi efektivni reseni jak prodat a6 za stale slusny prachy. Dalsi vec je ze llano ma dve rozdilna pole pusobnosti (NB/desktop), takze pokud chip nema vhodne provozni vlastnosti pro jeden segment, muze se pouzit v druhem.THANATOS píše:Akoze nie, praveze este viac alebo myslime na ine veci![]()
chybny 4modul BD mozes predat ako 3 modul alebo 2 modul.
chybne 4jadro Llano vies predat len ako 2 jadro lebo 3 jadro zatial neplanuju a Llano ma este aj IGP ak to je chybne tiez je problem. BD ak ma chybnu L3 tak sa uzatvori a ked ich budu mat dost, tak uvedu nove modely s mensou cache alebo rovno uzamknu aj moduly a predaju ako 3 modul.

tak tím je řečeno vše co se týká použití obou jader pro navýšení single thread performanceQ&A by John Fruehe:
1.A single thread can be processed by both cores of integers or is this impossible?
odpověď: no
2.For the near future, Will AMD add more int core into single module ? Eg: single module has 4 int core !
odpověď: That depends on how it scales. We would not add cores just to add cores. And in relation to “near future” the answer is no.
3.As far as i understand 2 threads on 2 modules can have separate L2 caches and (possibly) independent resource/memory access requests, but within 1 module it can be hardly possible.
Depending on the task, 1 thread may take up to 100% of L2 cache (and, possibly, other resources) for its own needs, which leaves the 2nd thread stalled and waiting for the data (or certain cases of I/O requests), which means in worst case scenario the performance of 2 threads on 1 module would reach close to 50% performance (in your numbers it would be 100% compared to 200% of 2 threads on 2 modules).
From the way i see such a problem, solving such bottlenecks cases would require better (deeper) I/O queuing for data and other requests, but that would again strike back with huge latencies of cache, which is a pain in current Phenoms. Was the increased cache latency problem ACTUALLY solved (in absolute numbers, not marketing ones) ?
odpověď: With 2 threads on the same module, you will not have one take all of the L2 cache. They share the cache, so that will not be a bottleneck.
4.Would it be possible for a module to use both integer cores to work on the same single thread?
odpověď: No, that is not possible.
5.Are there any improvements in single-threaded performance of memory-intensive server applications running on Bulldozer compared with the current Opteron processors ?
odpověď: We have answered that question many times. Single threaded performance will be greater. We are not stating anything about memory increases at this point, but we have said that there will be big improvements (and we already have leading memory performance.)

Tak já myslím, že to bylo jasné i před tím. Navíc dle 0xR by to stejně nemělo valný význam a já s ním jen souhlasím.del42sa píše: tak tím je řečeno vše co se týká použití obou jader pro navýšení single thread performance
IMHO si myslím, že tou tajnou zbraní myslí FMAC, který by teoreticky měl zdvojnásobit výkon FPU. Ovšem jen u aplikací, které s ním počítají.del42sa píše:... kde se píše že má FX ještě další "unikátní schopnosti" jako tajnou zbraň....
jen Flex FPU....
