Jetway radeon 9550ultra o/c 128mb

[t0m4s3]

jasne ze jadro ide cez 500 ked default je 500 kamosovu som dostal na 511 a pamate len tak od oka na 710 a myslim ze este mali rezervu...

[janis]

Takže ten Filozofův BIOS je tutově z ABITU 9600XT VIO - jen je upravená velikost pamětí - ABIT má 256 MB, jinak sedí do puntíku všechno mimo drobné úpravy časování:
ABIT
-- RaBiT v.1.6.1 build 347 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 53248 bytes, ROM len: 53248 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x118
> PCIR struct offs: 0x184
> CRC table offs: 0x1B0
> CLOCK table offs: 0x956
Core clock is 500.00 MHz
Memory clock is 300.00 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x1F0
MEM info: MC_CNTL(0x00000071), memory size = 256 Mb
> Memory config: 0x7180
> TV table offs: 0xC54A
Active TV type: 'NTSC'
> Multimedia table: at 0x64E, Rev.1
> Hardware table: at 0x63A, Rev.2
hw_a: 0x3502, hw_b: 0x0201
> DFP table offs: 0x65A
DFP table Ver.4, 2 preset(s)
TMDS_PLL(1FBB0155), freq = 130.00 MHz
TMDS_PLL(1FBB010F), freq = 200.00 MHz
> Connectors Layout table offs: 0x644
Conn0 type = VGA, DDC = VGA, DAC = Unknown
Conn1 type = DVI-I, DDC = DVI, DAC = Primary
ASIC init: 0x75 = 0x08, 0x74 = 0x92
-- ROM BIOS info --
Desc: RV360 PRO A198 VIVO TSOP BIOS
Info: V350AGP DGD1UN, RAAB616H.X01 v611 , 2004/03/09 12:07
Radeon family: Radeon 9600/9550/X600/X300 series
-- Parsing hardware scripts: --
> PLL script at 0x052C
> PLL2 script at 0x05E5
> INIT script at 0x02A4
> MEMORY script at 0x03FD
-- Found hardware registers values: --
> M_SPLL_REF_FB_DIV(0x03252C04) at 0x0551
> SCLK_CNTL(0x00007FF9) at 0x05AB
> MC_TIMING_CNTL(0x1B392323) at 0x0435
> MC_CNTL(0x00000071) at 0x03FF
> MCLK_CNTL(0x001F1212) at 0x0580
> MC_SDRAM_MODE_REG(0x31420042) at 0x044B
> MC_READ_CNTL_AB(0x0BBD0BBD) at 0x0322
> MC_REFRESH_CNTL(0x00009024) at 0x031C
> MC_CHP_IO_OE_CNTL_AB(0x2FF52FF5) at 0x042F
-- In BIOS memory timings --
tWL = 1.0
tCL = 4
tCMD = 0 clock
tSTB = equals tWrL + 1/2 clocks
tRcdRD = 6
tRcdWR = 3
tRP = 6
tRAS = 10
tRRD = 3
tR2W = CL + 3
tWR = 4
tW2R = 3
tW2Rsb = Use tWR Rule
tR2R = 2
MemRR = 24
tRFC = 22
tRBS = CL + 3.5
tERST = CL - 0.5
tQSREQ = CL - 0.5
tDQM = WL - 0.5
tDQS = WL - 0.5
tDQM_Adv = 1 clock earlier for WL 1 clock and more
tDQS_Adv = 1 clock earlier for WL 1 clock and more
-- Additional hardware info --
SDRAM Mode Register: 0x42
MCLK source select: MPLLCLK/2
SCLK source select: SPLLCLK/1
Chipset use A,B memory channels
SDRAM specific: 2**13 rows, 512 columns
SDRAM dynamic CKE is Enabled
-- User changes followed --

JW9550Ultra O/C Filozofa
-- RaBiT v.1.6.1 build 347 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 53248 bytes, ROM len: 53248 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x116
> PCIR struct offs: 0x184
> CRC table offs: 0x1B0
> CLOCK table offs: 0x966
Core clock is 500.00 MHz
Memory clock is 300.00 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x1F0
MEM info: MC_CNTL(0x00000069), memory size = 128 Mb
> Memory config: 0x6940
> TV table offs: 0xC55A
Active TV type: 'NTSC'
> Hardware table: at 0x63A, Rev.2
hw_a: 0x3502, hw_b: 0x0201
> DFP table offs: 0x64C
DFP table Ver.4, 2 preset(s)
TMDS_PLL(1FBB0155), freq = 130.00 MHz
TMDS_PLL(1FBB010F), freq = 200.00 MHz
> Connectors Layout table offs: 0x644
Conn0 type = VGA, DDC = VGA, DAC = Unknown
Conn1 type = DVI-I, DDC = DVI, DAC = Primary
ASIC init: 0x75 = 0x08, 0x74 = 0x92
-- ROM BIOS info --
Desc: RV360 PRO A198 VIVO TSOP BIOS
Info: V350AGP DGD1UN, ra8300.x01 v611 , 2003/01/05 21:27
Radeon family: Radeon 9600/9550/X600/X300 series
-- Parsing hardware scripts: --
> PLL script at 0x052C
> PLL2 script at 0x05E5
> INIT script at 0x02A4
> MEMORY script at 0x03FD
-- Found hardware registers values: --
> M_SPLL_REF_FB_DIV(0x03252C04) at 0x0551
> SCLK_CNTL(0x00007FF9) at 0x05AB
> MC_TIMING_CNTL(0x1A28B323) at 0x0435
> MC_CNTL(0x00000069) at 0x03FF
> MCLK_CNTL(0x001F1212) at 0x0580
> MC_SDRAM_MODE_REG(0x31420042) at 0x044B
> MC_READ_CNTL_AB(0x0BBD0BBD) at 0x0322
> MC_REFRESH_CNTL(0x00009024) at 0x031C
> MC_CHP_IO_OE_CNTL_AB(0x2FF52FF5) at 0x042F
-- In BIOS memory timings --
tWL = 1.0
tCL = 4
tCMD = 0 clock
tSTB = equals tWrL + 1/2 clocks
tRcdRD = 6
tRcdWR = 3
tRP = 6
tRAS = 12
tRRD = 2
tR2W = CL + 3
tWR = 3
tW2R = 2
tW2Rsb = Use tWR Rule
tR2R = 2
MemRR = 24
tRFC = 22
tRBS = CL + 3.5
tERST = CL - 0.5
tQSREQ = CL - 0.5
tDQM = WL - 0.5
tDQS = WL - 0.5
tDQM_Adv = 1 clock earlier for WL 1 clock and more
tDQS_Adv = 1 clock earlier for WL 1 clock and more
-- Additional hardware info --
SDRAM Mode Register: 0x42
MCLK source select: MPLLCLK/2
SCLK source select: SPLLCLK/1
Chipset use A,B memory channels
SDRAM specific: 2**12 rows, 512 columns
SDRAM dynamic CKE is Enabled
-- User changes followed --

Bomba, co? A to jsem prolezl asi 10 různých BIOSů od různých značek pro R9550,9600Pro a XT, co se daly sehnat na webu - žádný se tak neshoduje a hlavně - všechny ostatní mají organizaci paměti 2**12 rows, 256 columns a tyhle BIOSy mi s ramBIOSem nejely - na 9550 od JW potřebujeme 2**12 rows, 512 columns.
Mám slíbenej BIOS od t0m4s3e, jestli se k tomu dostane.Pak ho vrazím na web i s ostatníma a utility pro BIOSy a grafiky.