PCTuning fórum

yuri.cs píše:April
3.0 GHz v rev.A0 (napr. BD ES rev.A1 mel frekvence 2.3/2.7 GHz)
Summit Ridge string misto AMD Eng Sample (Zeppelin ES, nebo tak)

TSMC also said he realized the tapeout last month of a "CPU" with two memory cells HBM2.

DOC_ZENITH píše:Ty čísla spotřeby v idle jsou naprosto mimo mísu. Jen NB v chipsetu u 990FX v idle žere více jak celej CPU intelu s aktivními C states. Na takhle nízkej odběr jsem se u celé platformy u FX nikdy nedostal u žádného z testovanách PC.

I have no in-depth information regarding AM4, but based on the known facts it is not too far fetched that the socket itself might be limited to quite low maximum CPU plane power draw.

AM3+ has 940 pins installed and the diameter of each pin is 0.3mm. 170 of these pins are designated for VDDCR (i.e CPU core power). In order to mount 1331 pins to a substrate with same dimensions (40x40mm), they need to reduce the pin pitch from 1.27mm to ~1.07mm. This would mean AM4 would be using essentially a 37x37 pin arrangement instead of the 31x31 used on AM3/+. The resulting pin diameter would be around 0.25mm.

A single pin with 0.3mm diameter (0.07mm² CSA) can carry around 1.49A of current. AMD themselves rate the pins used on AM3/+ and FM2/+ packages for 1.50A in temperatures at or below 30°C. Meanwhile a single pin with 0.25mm diameter (0.049mm² CSA) can carry around 1.15A.

On AM4 many of the pins will be reserved for display outputs and peripherals, while AM3/+ socket did not use any for these purposes. Additionally the common socket design dictates that the socket must support APUs, which means that there must be a high current secondary power plane available.

Even the current generation iGPUs found in Steamroller and Excavator APUs can consume excess 40W at stock and significantly more when overclocked. This means that on AM4 there must be at least 150 (75 VDD_SoC, 75 VSS) reserved for the secondary power plane alone (incl. safety margins). On AM4 CPUs VDD_SoC most likely powers the CNB interface (core northbridge and possibly the L3 cache).

For AM4 I expect to see around 2.5:1 ratio in VDDCR and VDD_SoC power pins. On AM3+ the ratio was 12.1:1 and on FM2+ 3.333:1.

Despite I don't expect first generation Zen CPUs to have basically any margin left for overclocking, I certainly hope AMD hasn't made too grave compromises when designing the socket infrastructure.

Maor píše:A ZEN se bude dělit o kapacitu s Polaris, v čemž vidím velké riziko odložení.