PCTuning fórum

del42sa píše: ↑stř 1. pro 2021, 11:10 https://www.hardwaretimes.com/amd-zen-3 ... nt-in-jan/

AMD Zen 3D V-Cache Based Ryzen CPUs Expected to Land in Feb-March (Announcement in Jan)

DOC_ZENITH píše: ↑čtv 2. pro 2021, 18:18 Pokud AMD bude pokračovat v chiplet designu, a pokud bude IF zpětně kompatibilní (mezi ZEN2/3 je) tak by šlo vydat ZEN4 s DDR4 a i ZEN3 s DDR5, o tom jaké bude mít CPU DDR a PCI-E rozhoduje pouze northbridge a ten lze nyní měnit separé.

Gagy - Tvé argumenty samo sebou zám, ale stil "největší zisk only" může vést k tom uže sami sebe vytlačej z různejch trhů. Ano Epyc platí nejvíce ale samo sebe defakto vyklidili z laptopů, APu jsou cenově nesehnatelný a na Alder by měli odpovědět a to teď. Vcache už taky maj teď jen jde zatim jen do Eypců. Každopádně na Sapphire-rapids už budou muset odpovědět. Too late hlavně proto že papírově ZEN3 s vcache release date vypadá na méně jak půl roku od ZEN4.

alienGT píše: ↑čtv 2. pro 2021, 21:40 A uz se vi, zdali ZEN4 bude mit hned od startu V-cache nebo chcou nejdrive low cache verzi a teprve pozdeji prijde ZEN4 v-cache stejne jako u predesle generace?

Sobo píše: ↑čtv 13. led 2022, 14:39 Z pohledu AMD je samozrejme pochopitelne, ze to chce co nejvic rvat do Epicu, kde ma nejspis podstatne vyssi marzne nez u desktopovych Ryzenu, ale pro zakazniky to nevyzniva zrovna pozitivne. Prijde to pozde, bude to blbe dostupne a pravdepodobne dost drahe. Vzhledem k tomu, ze to hypovali uz od cervence 2020, tak imo docela fail...

In a performance teaser, tech outlet, Chips and Cheese has posted the first performance metrics highlighting the 3D V-Cache design of the AMD EPYC Milan-X CPU. The performance was compared against the standard EPYC 7763 Milan and EPYC 7V73X Milan-X CPUs. Despite the fact that there is three times the cache on the Milan-X chips, it was able to maintain almost similar latency with the former Milan CPU. Even the 3-4 cycle latency increase is negligible compared to the amount of LLC you are getting with this behemoth of a server chip.

All I have to say is good job AMD, this minimal latency increase of 3 to 4 cycles is downright amazing considering that this is three times the L3 of standard Milan. Now the clock speed of Milan-X is a little lower on paper; however, it does appear that Milan-X is boosting better than standard Milan, which effectively negates the slight cycle increase of V-Cache.

What is interesting here is that increasing the cache size by increasing the set count looks pretty cheap in terms of added latency. Zen 1 to Zen 2 doubled the size of each slice and only increased the latency cost by about 5 cycles. Similarly, Zen 3 to Zen 3 with V-Cache tripled the slice size but only added 3 to 4 cycles to the latency where as the move from Zen 2 to Zen 3 which unified the 2 16MB L3s on a CCD into a single 32MB L3 added 7 to 8 cycles to the L3 latency; now how much of that extra latency was due to AMD preplanning for V-Cache, we simply can not know. But even considering that, it looks like it is cheaper latency wise to increase the set count per cache slice then to unify 2 separate caches into one single unified, same size, cache.

Again, the L3 is the interesting section here because comparing AMD’s L3 to Intel’s L3 shows no contest between the two in terms of latency. On average, AMD’s L3 latency is 24-28 cycles faster then Intel’s which is a very large difference. This is due to the mesh topology that Intel uses on server CPUs versus AMD’s ring topology and the tradeoffs between the two topologies. Ring being both lower latency and higher bandwidth compared to Mesh but Mesh is more scalable for a monolithic CPU compared to a Ring topology.

This is a more interesting result then the OpenSSL result because while the performance difference is only 7.6% in favor of Milan-X, it is also clocking about 5% lower than Milan which means that iso-clock V-Cache is giving around a 12.5% performance increase in this test.